1. Field of the Invention
The present invention relates to signal processors for imaging sensors of the type that employ clamp-sample-and-hold (C-S/H) circuits and, more particularly, a signal processor that employs a resettable C-S/H (RC-S/H) circuit that eliminates sequential pixel crosstalk while improving noise immunity.
2. Description of the Prior Art
A charge-coupled device (CCD), among other imaging sensors, may be used to generate video output signals corresponding to a particular sensed image. These video output signals must be recovered in a manner that preserves the characteristics of the image sensed by the CCD array. Heretofore, signal processing circuits have been used to recover the video signals generated by imaging sensors. Such signal processing circuits include the standard C-S/H correlated double sampling (CDS) processor, or more complex CDS processors such as the gated integrator. Problems associated with recovering video imaging signals include sequential pixel crosstalk and video output noise.
The C-S/H CDS design, which is the basis for the present invention, is a relatively simple circuit that utilizes a resistive and capacitive (RC) combination to filter video output noise from the true video signal. However, the bandwidth selected for the RC filter reflects a compromise between noise rejection and sequential pixel crosstalk. Hence, sub-optimal noise rejection performance is often the price paid for an acceptably low level of sequential pixel crosstalk.
The gated integrator and other more intricate types of CDS processors are inherently free of crosstalk between sequential video imaging pixels. However, the circuitry required to implement these designs is considerably more complex than that of the basic C-S/H processor. Therefore, these types of CDS processors are often deemed unacceptable for certain applications.